Regviz

Renesas Electronics /R7FA6M1AD /BUS /CS1WCR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CS1WCR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Renesas Electronics/R7FA6T1AD/BUS/CS1WCR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (others)CSPWWAIT 0Reserved0 (others)CSPRWAIT 0Reserved0 (others)CSWWAIT0Reserved 0 (others)CSRWAIT0Reserved

CSRWAIT=others, CSPWWAIT=others, CSWWAIT=others, CSPRWAIT=others

Description

CS1 Wait Control Register 1

Fields

CSPWWAIT

Page Write Cycle Wait Select NOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.

0 (0x0): No wait is inserted.

0 (others): Wait with a length of CSPWWAIT clock cycle is inserted.
Reserved

These bits are read as 00000. The write value should be 00000.
CSPRWAIT

Page Read Cycle Wait Select NOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.

0 (0x0): No wait is inserted.

0 (others): Wait with a length of CSPRWAIT clock cycle is inserted.
Reserved

These bits are read as 00000. The write value should be 00000.
CSWWAIT

Normal Write Cycle Wait Select

0 (0x00): No wait is inserted.

0 (others): Wait with a length of CSWWAIT clock cycle is inserted.
Reserved

These bits are read as 000. The write value should be 000.
CSRWAIT

Normal Read Cycle Wait Select

0 (0x00): No wait is inserted.

0 (others): Wait with a length of CSRWAIT clock cycle is inserted.
Reserved

These bits are read as 000. The write value should be 000.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data